PIC17C42
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC17C42
Bank 0 | Bank 1 | Bank 2 | Bank 3
--- | --- | --- | ---
SFR 0x000 - 0x017 24 bytes Common 0x018 - 0x0FF 232 bytes | SFR 0x100 - 0x117 24 bytes Mirrored 0x118 - 0x1FF 232 bytes | SFR 0x200 - 0x217 24 bytes Mirrored 0x218 - 0x2FF 232 bytes | SFR 0x300 - 0x317 24 bytes Mirrored 0x318 - 0x3FF 232 bytes
It is possible that this colums is inaccurate due to the mirrored-SFRs.

SFR 24 bytes GPR 0 bytes Common 232 bytes Mirrored 0 bytes Unimplemented 0 bytes | SFR 24 bytes GPR 0 bytes Common 0 bytes Mirrored 232 bytes Unimplemented 0 bytes | SFR 24 bytes GPR 0 bytes Common 0 bytes Mirrored 232 bytes Unimplemented 0 bytes | SFR 24 bytes GPR 0 bytes Common 0 bytes Mirrored 232 bytes Unimplemented 0 bytes
It is possible that this colums is inaccurate due to the mirrored-SFRs.

Special Function Register.

General-purpose RAM.

Common RAM.

Mirrored RAM.

In this place no RAM.

This page generated automatically by the device-help.pl program (2014-09-27 07:53:47 UTC) from the 8bit_device.info file (rev: 1.21) of mpasmx and from the gputils source package (rev: svn 1103). The mpasmx is included in the MPLAB X.