PIC16C773
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC16C773
CONFIG (address:0x2007, mask:0x3F7F, default:0x3F7F)
FOSC -- Oscillator selection bits (bitmask:0x0003)
FOSC = LP | 0x3FFC | LP oscillator.
FOSC = XT | 0x3FFD | XT oscillator.
FOSC = HS | 0x3FFE | HS oscillator.
FOSC = RC | 0x3FFF | RC oscillator.
WDTE -- Watchdog Timer Enable bit (bitmask:0x0004)
WDTE = OFF | 0x3FFB | WDT disabled.
WDTE = ON | 0x3FFF | WDT enabled.
PWRTE -- Power-up Timer Enable bit (bitmask:0x0008)
PWRTE = ON | 0x3FF7 | PWRT enabled.
PWRTE = OFF | 0x3FFF | PWRT disabled.
BOREN -- Brown-out Reset Enable bit (bitmask:0x0040)
BOREN = OFF | 0x3FBF | BOR disabled.
BOREN = ON | 0x3FFF | BOR enabled.
BODENV -- Brown Out Voltage (bitmask:0x0C00)
BODENV = 45 | 0x33FF | VBOR set to 4.5V.
BODENV = 42 | 0x37FF | VBOR set to 4.2V.
BODENV = 27 | 0x3BFF | VBOR set to 2.7V.
BODENV = 25 | 0x3FFF | VBOR set to 2.5V.
CP -- Code Protection bits (bitmask:0x3330)
CP = ALL | 0x0CCF | All memory is code protected.
CP = 75 | 0x1DDF | 0400h-0FFFh code protected.
CP = 50 | 0x2EEF | 0800h-0FFFh code protected.
CP = OFF | 0x3FFF | Code protection off.

This page generated automatically by the device-help.pl program (2016-01-02 14:08:22 UTC) from the 8bit_device.info file (rev: 1.27) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.